Design of High Speed Flip-Flop Based Frequency Divider for GHz PLL System: Theory and Design Techniques in 250nm CMOS Technology

Design of High Speed Flip-Flop Based Frequency Divider for GHz PLL System: Theory and Design Techniques in 250nm CMOS Technology Harsh Joshi, Prof. Sanjeev M.Ranjan, Prof. (Dr). Vijay nath 1 2 Department of Electronics and Telecommunication 1 2 Disha Institute Of Management & Technology, Raipur, India Department of Electronics and Telecommunication, BIT Mesra, Rachi (J.H) [email protected], [email protected],[email protected] AbstractThe coexistence of different cellular system demands reconfigurable mobile terminals. For greater degree of application such as Text, graphics, audio and games etc are required to handle by modern handset. These demands can be fulfilled by integrating some complementary technologies such as WLAN or Bluetooth, UWB for high bandwidth local or personal services and 2G – 3G standards for voice low data rate communication with wide area coverage together in same handset. The Purpose of this paper is to present four designs of high Frequency, Broadband Frequency divider. The designs are viewed for firmness across process variations and high operating frequencies. These designs are chosen to fulfill above necessities for this reason here we have selected four design topologies that has less circuit component thereby reducing overall power consumption of the circuit. Circuit also designed so that it is not continuous involved in dividing the input frequency. Wherever signal is applied it is in action thereby minimizing the overall power consumption.